The present invention relates to a process for selectively coating certain areas of a composite surface with a conductive film, to a process for fabricating interconnects in microelectronics, and to processes and methods for fabricating integrated circuits, and more particularly to the formation of networks of metal interconnects, and also to processes and methods for fabricating Microsystems and connectors.
In what follows, the prior art has intentionally been restricted to the field of microelectronics, as this is representative of the exacerbation of the technical difficulties in obtaining selective controlled coatings, as the demand, in terms of more rapid processing and ever finer etching, is becoming more pressing, especially for the production of self-aligned barriers on the copper tracks obtained after chemical-mechanical polishing (CMP) in damascene and dual damascene processes. A person skilled in the art may therefore readily transpose these problems to other applications such as Microsystems or connectors, as the problem is the same but simply on a different scale.
Integrated circuits are fabricated by forming discrete semiconductor devices on the surface of silicon wafers. A network of metallurgical interconnection is then established on these devices so to establish contacts between their active elements and to produce, between them, the wiring needed to obtain the desired circuit. A system of interconnects consists of several levels. Each level is formed by metal lines and these lines are connected together by contacts called “interconnect holes” or “vias”.
The response time of an interconnect circuit is characterized by a constant RC, which corresponds roughly to the resistance R of the metal levels multiplied by their capacitive coupling represented by the constant C, mainly determined by the nature of the dielectric that separates the lines.
From the metallization standpoint, the response time of the interconnects is therefore reduced by reducing the resistance of the lines. It is for this reason that copper has been introduced into the more recent processes, replacing the more resistive and less electromigration-resistant aluminium. However, the introduction of copper raises several difficulties:                it is necessary to use a damascene-type architecture in which the dielectric is deposited beforehand and then etched, before filling with copper and chemical-mechanical polishing. To meet the requirements of the microelectronics industry, very fine geometries (trench and via dimensions of less than 0.1 μm) having high AR or aspect ratio (AR about 4/1 for the trench and via dual damascene structure in its entirety) need to be able to be effectively filled;        it is also necessary to prevent the diffusion of copper through the dielectric into the silicon, since copper is a poison for the active components. To do this, it is necessary to employ effective barriers, which in addition provide a solid interface, that is to say good adhesion between the copper and the dielectric.        
In the damascene process, the metallization is carried out in three main steps:                step 1: deposition of a thin copper diffusion barrier layer, by PVD (Physical Vapour Deposition) or CVD (Chemical Vapour Deposition);        step 2: deposition of a thin copper tie layer, which also serves as a nucleation layer for the next deposition; and        step 3: electroplating with copper, during which the substrate acts as a cathode on which the metal is deposited from a solution of its salt.        
Once copper has been deposited, the excess copper is removed by CMP. The surface obtained is then in the form of a composite surface comprising alternating bands of copper and dielectric, each of the copper bands being bordered by a very fine semiconductor band, a vestige of the barrier layer installed in the trenches before filling with copper, and sliced off during the polishing. After these copper and dielectric bands have formed, they are then conventionally encapsulated with a uniform layer of the SiC or SiCN type, covering the entire composite surface, and serving as a copper diffusion barrier.
Now, these coatings are insulating, but they have a relatively high dielectric constant, which increases the capacitive coupling between copper lines. In addition, recent studies have shown that the interface between the copper lines and this insulating barrier is a weak point of the multilayer, from which catastrophic defects are initiated during the operation of the circuits (electromigration, crack initiation, etc.) (L. Peters, Semiconductor International, 2002, consultable on the Internet at the following address: http:/www.reed-electronics.com/semiconductor/article/CA224702?text-capping&stt=001&).
To improve the isolation of the copper lines and to increase the reliability of the interconnects for sub-65 nm technologies, one solution consists in using a barrier of the metal type, selectively deposited on the copper. This involves in fact depositing a copper diffusion barrier on the fourth side of the trenches, so as to completely enclose the copper lines in a “box”, from which they can no longer emerge. Provided that this encapsulation barrier is highly adherent to the copper, the mobility of the copper at the copper/encapsulation barrier interface is greatly reduced and, consequently, the electrical current supported by the copper line, with no degradation, is higher and the resistance to electromigration increased. To do this, the encapsulation barrier must be self-aligned with the subjacent copper so as to avoid leakage currents between neighbouring copper lines. The approaches envisaged for this selective deposition are the selective chemical vapour deposition (CVD) of tungsten and the selective electroless plating with metal alloys. Metallic materials are therefore preferred because (i), in general, metals are considered to be more adherent to copper than dielectrics and (ii) the aforementioned selective techniques can be carried out for metals or alloys.
Electroless plating involves a reduction reaction in which a metal salt is reduced to metal, catalyzed on the surface of another metal. The metal salt solutions allowing metals to be deposited without the intervention of an external current or voltage source are called metallization solutions or electroless solutions.
The metal deposits that can exhibit barrier properties are those based on refractory metals such as tungsten, cobalt, nickel or their alloys and mixtures, optionally with certain additive elements such as phosphorus or boron. In particular, CoWP, CoWB and NiMoP deposits are currently employed, these all having in common the fact that they are obtained from electroless solutions containing especially cobalt salts, tungsten salts, nickel salts, molybdenum salts, etc., respectively, necessary for the barrier material, and also a reducing agent, for example dimethylaminoborane (DMAB). These reactions are in general catalyzed by transition metals (they are in particular autocatalytic). Such solutions are described for example in U.S. Pat. No. 5,695,810.
In theory, it is therefore possible to imagine that the copper of the metal lines could provide this catalytic action: the deposition would then take place exclusively on the surface of the copper lines. However, it is found in practice that copper is insufficiently catalytic to allow good growth of the deposit under these conditions.
To remedy this insufficiency, it is possible to activate the copper tracks, by attaching—selectively on these tracks—aggregates of other transition metals having superior catalytic properties. This is the case, for example, with palladium, platinum, cobalt, nickel or molybdenum, which are good catalysts for depositing metals in general.
Among these transition metals, palladium takes special place, given that the standard potential of its Pd(II)/Pd0 pair is greater than that of the Cu(II)/Cu0 pair. The result, in the presence of metallic copper, is that the Pd(II) ions are spontaneously reduced, to give a metallic palladium deposit on the copper (which itself will have been slightly oxidized on the surface). This property of palladium and copper standard potentials therefore results in spontaneous deposition—in principle selective deposition—of palladium on the copper tracks. It is this property that has resulted in the appearance of processes for constructing self-aligned barriers called “palladium activation” barriers, which comprise a step of forming palladium aggregates on the copper lines followed by a step of locally catalyzed growth of the metal barrier layer. In these processes, it is preferred to have palladium in the form of aggregates distributed over the copper lines, rather than in the form of a uniform layer, especially because:                (i) this makes it possible to increase the palladium/electroless solution contact area, and therefore locally increase the kinetics more effectively;        (ii) this makes it possible to minimize the amount of palladium present—in the end—at the interface between the copper and the metal barrier layer (it is in fact considered that palladium diffuses easily into copper, and may be the cause of degradation of its electrical conduction properties).        
However, this technique is not entirely satisfactory either, insofar as several problems in the activation of the copper tracks by palladium are observed:                1) during the spontaneous reduction of the Pd(II) ions on the copper, the palladium deposit formed is conductive. This deposition can therefore continue by itself and give—not aggregates—but more bulky deposits, by the “mushroom effect”. This means that the period of time in contact with a Pd(II) solution is a crucial parameter and that, if this time is too long, this necessarily results in a deposit on each line which is sufficient for it to join that of the neighbouring line and produce a short circuit. This is a source of instability in the process;        2) even before reaching these extremes, the palladium ions exhibit adsorption that is rarely completely specific and, what is more, is dependent on the nature of the dielectric present between the copper lines. This non-specific adsorption on the dielectric rather than on the copper does not entail per se the formation of metallic palladium on the dielectric (between the copper lines), but such becomes the case if this non-specific adsorption takes place in a region close to the copper line. In addition, the electroless solutions then used to produce the selective barrier deposits contain reducing agents which may convert the palladium ions adsorbed on the surface of the dielectric into palladium aggregates which will themselves catalyze, at the wrong point, the growth of the metal barrier and cause a short circuit. In all these cases, lateral growth may take place, for the same reasons as in point 1) above, and result in a short circuit between the lines. It should be noted that this effect, even though already present on non-porous dielectrics of the SiO2 or SiOC type, is even more pronounced when the dielectric is a porous material of low permittivity (K), in which there may be not only adsorption but also insertion:        3) in general, quite a strong dependence of the palladium activation is observed as a function of the CMP step that precedes the formation of the self-aligned barrier. Apart from the fact that this CMP step does not necessarily allow planarization, clearly revealing the copper lines relative to the dielectric lines, a number of CMP residues remain adsorbed on the copper tracks and cover them with a layer that prevents their reactivity from being expressed, and especially their redox reactivity. In certain cases, complete absence of activation by the palladium solutions, such that the copper lines are encumbered, may be observed; and        4) once the palladium aggregates have been deposited on the copper tracks, the surface thus activated is brought into contact with a suitable electroless solution. Now, it turns out that these palladium aggregates become detached from the surface of the copper tracks and go into the said solution, where they will fulfil their catalytic role with increased vigour (since reactions and catalyses are always more rapid within a volume than on a surface, for basic collision frequency factor reasons involved in the kinetic constants). Since the reactions of metal aggregate formation in a volume are in general autocatalytic, the immediate consequence of this desorption is the almost complete consumption of the electroless solution, this being in general very rapid or even instantaneous.        
Thus, even though palladium does have a number of advantages owing to the value of its standard redox potential, this is insufficient to allow real selectivity of the deposition of the palladium aggregates, especially on very fine structures (structures of 0.2 μm and below, that is to say etching sizes compatible with integrated circuit technological generations of 130 nm and below).
Changing to aggregates of types other than palladium aggregates essentially entails the same types of drawbacks, to which is added the fact that it is not possible a priori to deposit them solely through their reduction by copper since the standard redox potential of their M(x)/M0 pair (x=I or II and M=Co, Ni, Mo, W, etc.) is generally less than that of the Cu(II)/Cu0 pair. One then relies on the presence of a reducing agent (for example of the DMAB type) directly in the bath containing these ions, and of various activators which enhance the catalytic effect of the copper. Thus, the reduction of these ions may in principle take place throughout the electroless bath, but it remains catalyzed particularly at points plumb with the copper lines. In fact, this results in there being only a copper track cleaning step by way of activation (in general by an acid treatment) followed by a step of contacting with an electroless solution containing sufficient additives to enhance the catalytic effect of copper. The drawback of these alternatives is the intrinsic instability of electroless solutions, and in particular of those that must also contain agents for enhancing the catalytic effect of copper.
The inventors were therefore given the objective of providing a process meeting all these requirements, satisfying the aforementioned specifications and furthermore solving the many aforementioned problems of the prior art, especially for the fabrication of metal interconnects, integrated circuits or other microsystems.